The Oolite V9 is a highly integrated and feature-rich IEEE 802.11n 2x2 2.4/5 GHz system-on- a-Chip for advanced WLAN platforms. Which supposes 802.11n operations up to 144 Mbps for 20 MHz and 300 Mbps for 40 MHz respectively, and 802.11a/b/g data rates. It includes a MIPS 74Kc processor, PCI Express 1.1 Root Complex and Endpoint interfaces, five port IEEE 802.3 fast Ethernet Switch with MAC/PHY, one MII /RMII/RGMII interface, one USB 2.0 MAC/PHY, and external memory interfaces for serial flash, SDRAM, DDR1or DDR2, I2S/SPDIF- Out audio interface, SLIC VOIP/PCM interface, two UARTs and GPIOs that can be used for LED controls or other general purpose interface configurations.
The AR8327 supports many operating modes that can be configured using a low-cost EEPROM and /or the MDC?MDIO interface. The AR8327 also supports a CPU header mode that appends two bytes to each frame.
The AR8327 contains a 2 K-entry address lookup table that employs three per bucket to avoid hash collision and maintain non-blocking forwarding performance. The table provides read/write accesses from the serial and CPU interfaces; each entry can be configured as a static entry. The AR8327 supports 4K VLAN entries configurable as port-bases VLANs or 802.1Q tag-based VLANs.
The CPU can be detected frame with header to configure the switch register, the address lookup table, and VLAN and receive auto-cast MIB frames. The sixth port(port5) supports a PHY interface as a WAN port. The first port (port0) supports a MAC interface and can be configured in
MII_PHY or RMII_PHY mode to connect to an external management CPU or an integrated CPU in a
74Kc MIPS processor with 64KB I-Cache and 32KB D-Cache, operating at up 533 MHz
32KB D-Cache, operating at up to 533 MHz
External 16- or 32- bit DDR1,DDR2 operating at up to 200 MHz(400 M transfers/sec), or 16-
bit SDRAM memory interface operating at up to 200 MHz
NAND and SPI NOR Flash memory support
10/100 Ethernet Switch with five IEEE 802.3 Ethernet LAN ports
802.3az Energy Efficient Ethernet compliant
Hardware-based NAT&ACL accelerators for Ethernet interface
Both PCI Express 1.1 Root Complex and Endpoint interface supported simultaneously
One USB 2.0 controller with built-in MAC/PHY supports Host or Device mode
Boot from external CPU via PCIE, USB, xMII, eliminating need for external flash
I2S/SPDIF-out audio interface
SLIC for VOIP/PCM
One low-speed UART(115 kpbs), one high-speed UART(3 Mbps), and multiple GPIO pins for
general purpose I/O
Fully integrated RF Front-End including PAs and LNAs
Optional external LNA/PA
25 MHz or 40 MHz reference clock input
1.2 V switching regulator
Advanced power management with ddynamic clock switching for ultra-low power modes
409-pin BGA package
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